Direct-Mapped Cache

In a direct-mapped cache every memory block has exactly one line it can live in. That makes lookup trivially fast — and makes the tag/index/offset split the whole exam. Final Q3(b) asks you to diagram one and split the address.

1. The mapping rule

cache line=(block number)mod(number of lines)\text{cache line} = (\text{block number}) \bmod (\text{number of lines})

With 8 lines, blocks 12 and 20 both map to line 12mod8=412 \bmod 8 = 4 and 20mod8=420 \bmod 8 = 4 — so they collide: only one can sit in the cache at a time (that's the weakness direct-mapped trades away for speed).

Main memory (blocks) Cache (8 lines) block 0 →0 block 1 →1 block 2 →2 block 3 →3 block 4 →4 block 5 →5 block 6 →6 block 7 →7 block 8 →0 block 9 →1 block 10 →2 block 11 →3 block 12 →4 block 13 →5 block 14 →6 block 15 →7 block 16 →0 block 17 →1 block 18 →2 block 19 →3 block 20 →4 block 21 →5 block 22 →6 block 23 →7 line 0 (000) line 1 (001) line 2 (010) line 3 (011) line 4 (100) line 5 (101) line 6 (110) line 7 (111)
8-line direct-mapped cache. Blocks 12 (red) and 20 (green) both map to line 4 = 100₂ — a conflict.

2. Splitting the address

A byte address is carved into four fields (right to left):

Tagidentify block20 bitsIndexwhich line10 bitsBlk offword in block0.9 bitsBytebyte in word2 bits
Example: 32-bit address, 1024 lines, 1-word blocks → tag 20, index 10, byte offset 2.
FieldBitsPurpose
Byte offsetlog2(bytes/word)=2\log_2(\text{bytes/word}) = 2which byte inside the word (usually ignored for word accesses)
Block offsetlog2(words/block)\log_2(\text{words/block})which word inside the block
Indexlog2(lines)\log_2(\text{lines})selects the cache line (the “row” to look in)
Tagthe reststored with the line to confirm it's the block you want

3. The hit test

Use the INDEX to pick the cache line
Is the line’s valid bit = 1?
if 0 → MISS (nothing valid stored yet)
Does the stored TAG equal the address’s tag?
if no → MISS (a different block lives here)
HIT → return the word using the block offset
Direct-mapped lookup: valid AND tag-match ⇒ hit.
Cache hitvalid == 1 and Tag == address tag.
Cache missvalid == 0 or Tag ≠ address tag.

4. Live address decoder

Set the cache geometry, then type a byte address to see how it splits.

Field widths → tag 20, index 10, block offset 0, byte offset 2(sum = 32 = 32)
Address 52 = 00000000000000000000000000110100
→ tag 00000000000000000000 · index 0000001101 = line 13 · blk · byte 00
Section checklist
  • Line = block number mod number of lines; explain a conflict (12 & 20 → line 4).
  • Split any address into tag / index / block offset / byte offset.
  • State the hit condition: valid = 1 AND tag matches.