Direct-Mapped Cache
In a direct-mapped cache every memory block has exactly one line it can live in. That makes lookup trivially fast — and makes the tag/index/offset split the whole exam. Final Q3(b) asks you to diagram one and split the address.
1. The mapping rule
With 8 lines, blocks 12 and 20 both map to line and — so they collide: only one can sit in the cache at a time (that's the weakness direct-mapped trades away for speed).
2. Splitting the address
A byte address is carved into four fields (right to left):
| Field | Bits | Purpose |
|---|---|---|
| Byte offset | which byte inside the word (usually ignored for word accesses) | |
| Block offset | which word inside the block | |
| Index | selects the cache line (the “row” to look in) | |
| Tag | the rest | stored with the line to confirm it's the block you want |
3. The hit test
Use the INDEX to pick the cache line
Is the line’s valid bit = 1?
if 0 → MISS (nothing valid stored yet)
Does the stored TAG equal the address’s tag?
if no → MISS (a different block lives here)
HIT → return the word using the block offset
Cache hit ⇔
Cache miss ⇔
valid == 1 and Tag == address tag. Cache miss ⇔
valid == 0 or Tag ≠ address tag. 4. Live address decoder
Set the cache geometry, then type a byte address to see how it splits.
Field widths → tag 20, index 10, block offset 0, byte offset 2(sum = 32 = 32)
Address 52 =
→ tag
Address 52 =
00000000000000000000000000110100→ tag
00000000000000000000 · index 0000001101 = line 13 · blk — · byte 00Section checklist
- Line = block number mod number of lines; explain a conflict (12 & 20 → line 4).
- Split any address into tag / index / block offset / byte offset.
- State the hit condition: valid = 1 AND tag matches.