COD Ch.4 — Performance

1aShow the IAS memory formats (data and instruction).

1bIf IAS memory is increased by 2ⁿ times, what is the new address size?

\text{new rows} = 2^{12} \times 2^{n} = 2^{12+n} \;\Rightarrow\; \text{address} = (12 + n) \text{ bits}

The address grows to (12 + n) bits.

1cbigSubtract (M(08A)+M(08B)) from (M(08C)+M(08D)); write to M(08E). Assembly + machine code.

Assembly	Opcode	Address
LOAD M(08C)	0000 0001	0000 1000 1100
ADD M(08D)	0000 0101	0000 1000 1101
SUB M(08A)	0000 0110	0000 1000 1010
SUB M(08B)	0000 0110	0000 1000 1011
STOR M(08E)	0010 0001	0000 1000 1110

2abigFP made 5× faster. Benchmark = 40 s, FP = 15 s. Overall speedup?

\begin{aligned} \text{Unaffected} &= 40 - 15 = 25 \text{ s} \\ \text{New time} &= 25 + \frac{15}{5} = 25 + 3 = 28 \text{ s} \\ \text{Speedup} &= \frac{40}{28} = 1.43 \end{aligned}

Overall speedup ≈ 1.43×.

2bExpress BIPS (billion instructions per second) in terms of clock rate & CPI (and clock cycle time & CPI).

\begin{aligned} \text{BIPS} &= \frac{\text{IC}}{\text{execution time} \times 10^{9}} \\ &= \frac{\text{clock rate}}{\text{CPI} \times 10^{9}} \\ &= \frac{1}{\text{CPI} \times \text{clock cycle time} \times 10^{9}} \end{aligned}

Same form as MIPS but with $10^{9}$ instead of $10^{6}$ .

2cbigA: IC=10B, 4 GHz, CPI 1.0. B: IC=8B, 4 GHz, CPI 1.2. Higher BIPS? Faster?

\begin{aligned} \text{BIPS} &= \frac{\text{clock rate}}{\text{CPI} \times 10^{9}} \\ A&: \frac{4 \times 10^{9}}{1.0 \times 10^{9}} = 4.0 \text{ BIPS} &\qquad B&: \frac{4 \times 10^{9}}{1.2 \times 10^{9}} = 3.33 \text{ BIPS} \end{aligned}

\begin{aligned} \text{Exec time} &= \frac{\text{IC} \times \text{CPI}}{\text{clock rate}} \\ A&: \frac{10 \times 10^{9} \times 1.0}{4 \times 10^{9}} = 2.5 \text{ s} &\qquad B&: \frac{8 \times 10^{9} \times 1.2}{4 \times 10^{9}} = 2.4 \text{ s} \end{aligned}

A has higher BIPS (4.0), but B is faster (2.4 s < 2.5 s). The BIPS/MIPS pitfall again — trust execution time.

3aDraw all MIPS addressing modes.

3bbigConvert to MIPS (temp = $t0): temp=p[k+1]; p[k+1]=p[k-1]; p[k-1]=temp; p[k]=p[k-1]+p[k+1]. ($a0=p base, $a1=k)

Each int = 4 bytes, so p[k] is at $a0 + 4·k. Compute the three byte-offsets, then load/store:

# $t1 = 4*k
sll  $t1, $a1, 2          # 4*k
add  $t2, $a0, $t1        # &p[k]
lw   $t0, 4($t2)          # temp = p[k+1]
lw   $t3, -4($t2)         # p[k-1]
sw   $t3, 4($t2)          # p[k+1] = p[k-1]
sw   $t0, -4($t2)         # p[k-1] = temp
lw   $t4, -4($t2)         # p[k-1]  (now = old temp)
lw   $t5, 4($t2)          # p[k+1]  (now = old p[k-1])
add  $t6, $t4, $t5        # p[k-1] + p[k+1]
sw   $t6, 0($t2)          # p[k] = ...

Pattern: index → ×4 (sll 2) → base+offset → lw/sw with ±4 for k±1.

3cMax value of offset in lw $s1,offset($s2), and the machine instruction for it.

Offset is a signed 16-bit field → max = $2^{15} - 1 = 32767$ .

lw $s1, 32767($s2) — I-format encoding

Spring 2026 — Fully Solved

Q1 (CO1) — IAS

Q2 (CO3) — Amdahl & BIPS

Q3 (CO2) — MIPS