MIPS Addressing Modes

“Draw all MIPS addressing modes” (Q3(a)) — there are five — plus the branch/jump address arithmetic they’re built on.

The five modes

#	Mode	Example	Where the operand is
1	Register (R-type)	`add $s1, $s2, $s3`	in a register
2	Base / displacement	`lw $s1, 8($s3)`	memory at (register + offset)
3	Immediate	`addi $s1, $s2, 7`	a constant inside the instruction
4	PC-relative	`beq $s1, $s2, Label`	$\text{PC} + 4 + 4 \times \text{offset}$
5	Pseudodirect	`j Label`	target from the 26-bit field

Mnemonic: Register, Base, Immediate, PC-relative, Pseudodirect → “RBI-PP”.

How each is drawn

1. Immediate — operand = the field itself

2. Register — Registers[rd/rs/rt]

3. Base — + Register(rs) → Memory[reg + offset]

4. PC-relative — + PC → Memory[PC + offset]

5. Pseudodirect — : PC → Memory[(PC⁰⁴)::addr::00]

Branch address arithmetic

beq/bne $rs, $rt, Label are I-type. The 16-bit offset counts instructions (words), relative to the next instruction.

\text{branch destination} = (\text{PC} + 4) + 4 \times \text{offset}

\text{offset} = \frac{\text{branch destination} - \text{PC} - 4}{4}

PC is the 32-bit Program Counter — it holds the address of the instruction currently executing. Normally it advances by $\text{PC} = \text{PC} + 4$ ; if the branch is taken, $\text{PC} = (\text{PC}+4) + 4 \times \text{offset}$ .

Worked value (from the slides)

Given PC = 200, $s0 = 8, $s1 = 8, and beq $s0,$s1,Label with offset = 1: $s0 == $s1 → branch taken.

\text{New PC} = (\text{PC} + 4) + 4 \times \text{offset} = (200 + 4) + 4 \times 1 = 208

If the condition were false,

\text{PC} = \text{PC} + 4 = 204

instead. The offset field is the number of instructions between the branch and the target.

Encoding a branch (from the slides)

beq $s0, $s1, Label ($s0 = 16 = 10000, $s1 = 17 = 10001, offset = 1):

beq $s0, $s1, Label

Jump (J-type)

j Label uses word-relative addressing: the 26-bit field is a word address. Example j Label with Label at 100 bytes = 25 words → field = 25, op = 000010:

j Label (target word 25)