COD Ch.4 — Performance

M.1Draw the three MIPS instruction formats with field widths.

M.2Draw all five MIPS addressing modes with an example each.

M.3bigEncode: lw $s0,32($s1); add $s0,$s0,$s2; sw $s0,36($s1). (lw=100011, sw=101011, add funct=100000)

lw  $s0,32($s1) : 100011 10001 10000 0000000000100000
add $s0,$s0,$s2 : 000000 10000 10010 10000 00000 100000
sw  $s0,36($s1) : 101011 10001 10000 0000000000100100

$s0=16=10000, $s1=17=10001, $s2=18=10010; $32 = 100000_2$ , $36 = 100100_2$ in 16 bits.

M.4bigTranslate to MIPS with bne, then to machine code: if (i!=j) h=i+j; else h=i-j; (h=$s2,i=$s3,j=$s4).

      bne $s3, $s4, Else
      add $s2, $s3, $s4
      j   Exit
Else: sub $s2, $s3, $s4
Exit: ...

bne : 000101 10011 10100 0000000000000010
add : 000000 10011 10100 10010 00000 100000
sub : 000000 10011 10100 10010 00000 100010

bne offset = 2 (add and j sit between bne and Else).

M.5Convert sub $s0,$s1,$s2 to machine code. (opcode 000000, funct 100000, as given.)

M.6Address of the last byte and last word in MIPS-32.

$2^{32}$ bytes total. Last byte = $2^{32} - 1$ . Words are 4 bytes and aligned, so last word = $2^{32} - 4$ .

M.7Address of the last word in MIPS-64 (everything similar to MIPS-32).

Scaling the MIPS-32 relationship (address width = word width): 64-bit addresses, word = 8 bytes. Last byte = $2^{64} - 1$ ; last word = $2^{64} - 8$ . (If the word is kept at 4 bytes, last word = $2^{64} - 4$ — state the assumption.)

M.8Max value of offset in lw $s1,offset($s2), and the machine instruction for it.

Offset is a signed 16-bit field → max = $2^{15} - 1 = 32767$ .

lw $s1, 32767($s2)

M.9beq $s0,$s1,Label with PC=200, $s0=$s1=8, offset=1. New PC?

Equal → taken. $\text{PC} = (200+4) + 4 \times 1 = 208$ . If not taken, PC = 204.

MIPS — Practice