Module 5 & 6 — Pipelining

Why pipelining speeds up a processor, the 5 MIPS stages, pipeline registers, the three hazard types and their fixes, and the speedup / latency / throughput arithmetic — with a live pipeline diagram (Final Q2, slide f).

Sections

💡

What & Why

Pipelining as an assembly line, the 5 MIPS stages, and the latency vs throughput idea.

🏗️

Stages & Datapath

Each stage in detail, pipeline registers, and the single-cycle vs pipelined datapath.

⚠️

Hazards & Fixes

Structural, data and control hazards — each with an example and its solution (forwarding, stalls, prediction).

📐

Speedup & Timing

Speedup, latency and throughput formulas with the exact final-exam calculation worked out — plus a live calculator.

🎯

Practice

Pipeline exam problems with reveal-able solutions.

Quick summary

PIPELINING = overlap instruction execution like a laundry assembly line.
  Same LATENCY per instruction, much higher THROUGHPUT.

MIPS 5 STAGES:  IF → ID → EX → MEM → WB
  IF  Instruction Fetch     — read instr from memory, PC += 4
  ID  Instruction Decode    — decode + read registers from register file
  EX  Execute               — ALU operation / address calculation
  MEM Memory access         — load/store data memory
  WB  Write Back            — write result into the register file
PIPELINE REGISTERS (IF/ID, ID/EX, EX/MEM, MEM/WB) hold each stage's results
  so the next stage can use them one cycle later.

CLOCK:  pipelined clock = SLOWEST stage.  Single-cycle clock = whole instruction.

k stages, n instructions, tc = cycle time:
  Pipelined time   = (k + n − 1) × tc          [k−1 fill + n]
  Non-pipelined    = n × (k × tc)              (single-cycle: k·tc per instr)
  Speedup          = non-pipelined / pipelined  → approaches k for large n
  Latency (1 instr)= k × tc                     Throughput = n / total time

HAZARDS (stop the next instruction entering the pipe):
  STRUCTURAL — two instrs need the SAME hardware at once (e.g. one memory).
               Fix: duplicate the resource (separate instr/data memory).
  DATA       — an instr needs a result not yet written by an earlier instr.
               Fix: FORWARDING (bypass from a pipeline register); else STALL.
  CONTROL    — a branch's outcome isn't known when the next fetch happens.
               Fix: stall, branch prediction, or delayed branch.