Speedup, Latency & Throughput

Final Q2(b) is always a 5-stage timing calculation. Learn these four formulas and the one worked example below and you own the whole question.

1. The formulas (memorize)

Let

k

= number of stages,

n

= number of instructions,

t_c

= pipelined clock cycle time.

\begin{aligned} t_c \;(\text{pipelined clock}) &= \max(\text{stage times}) \\ \text{Single-cycle time / instr} &= \textstyle\sum(\text{stage times}) \\ \text{Non-pipelined total} &= n \times \textstyle\sum(\text{stage times}) \\ \text{Pipelined total} &= (k + n - 1)\times t_c \end{aligned}

Quantity	Non-pipelined	Pipelined
Total time (n instrs)	$n \sum t_i$	$(k+n-1)\,t_c$
Latency (1 instr)	$\sum t_i$	$k \times t_c$
Throughput (steady)	$1 / \sum t_i$	$1 / t_c$
Speedup	$\dfrac{\text{non-pipelined total}}{\text{pipelined total}} \;\to\; k \text{ as } n \to \infty$

Counter-intuitive but examined: pipelining makes a single instruction's latency worse (

k\,t_c \ge \sum t_i

) because every stage now takes a full clock. It wins only on throughput.

2. Worked example — Autumn 2025 Q2(b)

5-stage pipeline (IF, ID, EX, MEM, WB); each stage 2 ns except MEM which is 3 ns; execute 2000 independent instructions with no hazards.

Q2bbig(i) total pipelined time · (ii) speedup vs single-cycle · (iii) single-instruction latency both ways · (iv) throughput both ways.

Setup. $k=5$ , $n=2000$ . Sum of stages $= 2+2+2+3+2 = 11$ ns. Pipelined clock $t_c = \max = 3$ ns.

(i) Pipelined total

(k+n-1)\,t_c = (5+2000-1)\times 3 = 2004 \times 3 = \boxed{6012\ \text{ns}}

(ii) Speedup. Non-pipelined total $= n\sum t_i = 2000\times 11 = 22000$ ns.

\text{Speedup} = \frac{22000}{6012} \approx \boxed{3.66\times}

(iii) Latency (one instruction). Non-pipelined $= \sum t_i = 11$ ns; pipelined $= k\,t_c = 5\times 3 = 15$ ns. Pipelining raises single-instruction latency from 11 ns to 15 ns.

(iv) Throughput. Non-pipelined $= 1/11\,\text{ns} \approx 90.9$ million instr/s; pipelined $= 1/3\,\text{ns} \approx 333.3$ million instr/s. ≈ 3.7× the throughput.

3. Live calculator

Edit the stage times or the instruction count — everything recomputes.

Stage	IF	ID	EX	MEM	WB
time (ns)

Number of instructions (n)

Pipelined clock

t_c

= max stage = 3 ns · Single-cycle time/instr = Σ = 11 ns · k = 5
Non-pipelined total = 2000 × 11 = 22000 ns
Pipelined total = (5 + 2000 − 1) × 3 = 6012 ns
Speedup = 3.66× (ideal ceiling = k = 5)
Latency: non-pipelined 11 ns · pipelined 15 ns
Throughput: non-pipelined 90.91 · pipelined 333.33 (×10⁶ instr/s)

Section checklist

Pipelined clock = slowest stage; single-cycle time = sum of stages.
Pipelined total = (k + n − 1) · t_c; speedup → k for large n.
Latency gets worse; throughput gets better — state both.