Pipelining — What & Why

Pipelining is the big idea of Module 5. It doesn't make a single instruction finish faster — it makes the processor finish more instructions per second by overlapping them, exactly like an assembly line. This is Final Q2.

1. The laundry analogy

Four loads of laundry, each needing Wash → Dry → Fold → Store. Do them one whole load at a time and the machines sit idle most of the day. Instead, start washing load 2 the moment load 1 moves to the dryer. Nothing got faster — you just stopped letting hardware sit idle.

Overlapped laundry: as long as each step has its own resource, the loads stagger one step apart.

The one insight: as long as each stage uses separate hardware, the stages can all be busy at once — each working on a different instruction.

2. The 5 MIPS pipeline stages

Every MIPS instruction is split into the same five steps, one per clock cycle:

A MIPS pipeline filling up: by clock cycle 5 all five stages are busy — steady state.

#	Stage	Full name	What happens
1	IF	Instruction Fetch	Read the instruction from instruction memory; increment `PC = PC + 4`.
2	ID	Instruction Decode	Decode the opcode and read the source registers from the register file.
3	EX	Execute	The ALU does the arithmetic/logic, or computes a load/store address.
4	MEM	Memory access	Read (`lw`) or write (`sw`) data memory. Other instructions do nothing here.
5	WB	Write Back	Write the result back into the destination register.

Mnemonic: I Don't Eat Meat Wednesdays — IF · ID · EX · MEM · WB.

3. Latency vs throughput — say it precisely

The exam rewards the exact definitions. Learn the contrast:

Latency — the total time for one instruction to pass through all stages. Pipelining does not improve latency; if anything it adds a little (pipeline-register delay).

\text{Latency} = k \times t_c

k = number of stages,

t_c

= clock cycle time.

Throughput — how many instructions complete per unit time. This is what pipelining improves: in steady state one instruction finishes every cycle.

\text{Throughput} = \frac{n}{\text{total execution time}}

The headline result: an ideal

k

-stage pipeline is up to

k\times

faster than the non-pipelined version — it just takes

k-1

cycles at the start to fill the pipe.

4. Why the clock can run faster too

A single-cycle machine's clock must be long enough for the slowest whole instruction (e.g. lw touching all five stages ≈ 800 ps). A pipelined clock only needs to cover the slowest single stage (e.g. 200 ps). Shorter stages ⇒ faster clock ⇒ even more throughput.

	Clock period set by…	Example
Single-cycle	slowest instruction	800 ps
Pipelined	slowest stage	200 ps

Section checklist

Pipelining overlaps instructions; it improves throughput, not latency.
MIPS stages in order: IF · ID · EX · MEM · WB, and what each does.
Steady state = one instruction completes per clock cycle.
Pipelined clock = slowest stage; single-cycle clock = slowest instruction.