Exam-pattern questions. Try each before revealing — that's where the marks come from.
Concept
P-1smallDefine pipelining. Does it reduce the time for a single instruction?
Pipelining overlaps the execution of multiple instructions by dividing execution into stages, each using separate hardware, so several instructions are in different stages at once. No — a single instruction's latency is not reduced (it may even rise slightly); pipelining improves throughput (instructions completed per unit time).
P-2smallName the 5 MIPS pipeline stages in order and say what each does.
Stage
Action
IF
fetch instruction, PC += 4
ID
decode, read registers
EX
ALU operation / address calc
MEM
data memory read/write
WB
write result to register
P-3smallWhat are pipeline registers and why are they needed?
Registers placed between adjacent stages (IF/ID, ID/EX, EX/MEM, MEM/WB). Because several instructions occupy the pipeline at once, each stage's partial results must be saved for the next stage to use on the next clock cycle — that's what the pipeline registers hold.
Hazards
P-4bigExplain a structural hazard with an example, then give its solution.
A structural hazard occurs when two instructions in different stages need the same hardware resource in the same cycle. Example: with a single unified memory, in one cycle an early instruction is in MEM (data access) while a later one wants IF (instruction fetch) — both need the one memory. Solution: duplicate the resource — use a split cache (separate instruction memory and data memory), so IF and MEM never contend.
P-5bigadd $s0,$t0,$t1 followed by sub $t2,$s0,$t3. What hazard is this and how is it resolved without stalling?
A data hazard: sub needs $s0 in EX, but add has not reached WB yet. But add's result exists in the EX/MEM pipeline register right after its EX stage. Forwarding (bypassing) routes that value straight into sub's ALU input — no stall required.
P-6smallWhy does a load followed by a dependent instruction still need one stall even with forwarding?
A lw produces its value only after the MEM stage — one stage later than an ALU result. The dependent instruction needs it in EX, which arrives one cycle too early, so forwarding alone can't cover it: insert one bubble (stall), then forward.
Timing
P-7big5-stage pipeline, each stage 3 ns except MEM = 4 ns. For 1000 instructions: (a) speedup vs single-cycle, (b) throughput gain, (c) latency change. (Summer 2025 Q2b)
Σti=3+3+3+4+3=16ns,tc=max=4ns,k=5,n=1000
(a) Non-pipelined =1000×16=16000 ns; pipelined =(5+999)×4=4016 ns. Speedup=16000/4016≈3.98×.
(b) Throughput non-pipelined =1/16 ns⁻¹, pipelined =1/4 ns⁻¹ → 4× more instructions per second.
(c) Latency non-pipelined = 16 ns; pipelined =5×4=20 ns → latency increases by 4 ns (the price of pipelining).
P-8smallA k-stage pipeline runs a very large program. What is the maximum possible speedup, and why is it never quite reached?
Maximum speedup =k (one instruction finishing every cycle vs one every k cycles). It's never fully reached because of the k−1 fill cycles, unequal stage times, and hazards (stalls).