Stages & the Pipelined Datapath

A datapath question (“divide the MIPS execution into stages and diagram the pipelined datapath”) appears on the final. The trick is the pipeline registers between stages.

1. Each stage in detail

IF — Instruction Fetch

Instruction memory + PC. Read the instruction at PC; compute PC + 4.

IF/ID

ID — Instruction Decode

Control unit decodes; register file reads the two source registers.

ID/EX

EX — Execute

ALU computes the result, or the effective address for lw/sw.

EX/MEM

MEM — Memory Access

Data memory read (lw) or write (sw). ALU-only instructions idle here.

MEM/WB

WB — Write Back

Result written into the destination register in the register file.

The four arrows are the four pipeline registers — each carries a stage's outputs to the next stage.

2. Pipeline registers — the key to overlap

In a pipeline, five instructions are in flight at once, each in a different stage. Each instruction's partial results (the fetched instruction, register values, the ALU output…) must be remembered so the next stage can use them on the next clock edge. That's the job of the four pipeline registers:

Named for the two stages they sit between. They are clocked every cycle, holding each stage's output for exactly one cycle.

Naming rule: a pipeline register is named PREV/NEXT — the stage that writes it and the stage that reads it. So ID/EX holds what ID produced for EX to consume.

3. Single-cycle vs pipelined datapath

The datapath hardware is nearly the same. The difference: the pipelined version inserts a register after every stage, turning one long combinational path into five short clocked segments.

Single-cycle datapath

One instruction flows through PC → InstrMem → Registers → ALU → DataMem → Registers in a single clock cycle. The clock must be long enough for the whole chain.

Pipelined datapath

The same chain is cut into 5 segments by IF/ID, ID/EX, EX/MEM, MEM/WB. Each segment runs in one (short) cycle, and five instructions occupy the five segments simultaneously.

The staircase, labelled with the datapath resource used

Column CC5 shows all five resources in use at once: instr-mem (IF), reg-read (ID), ALU (EX), data-mem (MEM), reg-write (WB).

Read/write split in one cycle. Notice WB (register write) and ID (register read) can line up in the same cycle for different instructions. MIPS handles this by writing the register file in the first half of the cycle and reading in the second half — so the read sees the fresh value.

Section checklist

List the 5 stages and the hardware each uses.
Name the 4 pipeline registers and say why they exist (carry results forward).
Explain the single-cycle → pipelined change: insert a register after each stage.