Live IAS Assembler
Type IAS assembly on the left; the 8-bit opcode + 12-bit address encoding appears on the right, updating as you type. Comments after ; are ignored.
Load a sample:
Supported: LOAD/ADD/SUB (incl. |M(X)|, −M(X)), STOR, MUL, DIV, LSH, RSH, LOAD MQ, JUMP variants. Address in hex, e.g. M(08B).
| Instruction | Opcode | Address (12) |
|---|---|---|
| LOAD M(08C) | 00000001 | 0000 1000 1100 |
| SUB M(08A) | 00000110 | 0000 1000 1010 |
| SUB M(08B) | 00000110 | 0000 1000 1011 |
| STOR M(08D) | 00100001 | 0000 1000 1101 |
Reminder: two 20-bit instructions pack into one 40-bit memory word — left instruction = bits 0–19, right instruction = bits 20–39.