IAS Memory & Formats

Everything for “calculate the memory size” and “show the memory formats” — plus the address-width formulas the memory-scaling questions rely on.

The memory

4096 storage locations (rows), addressed M(0) … M(4095).
Each row / word is 40 bits wide.
Address line = 12 bits, because $\log_2(4096) = 12$ .

The two master formulas

\text{address line width} = \log_2(\text{number of rows}) \text{ bits}

\text{number of rows} = 2^{\text{address line width in bits}}

Reading memory: put a row number on the address lines → the word stored there comes out on the data lines. Example: address 100 (binary) → out comes the 40-bit word 34673497A2H.

Rows	Address width = $\log_2(\text{rows})$
4 (00…11)	2 bits
8 (000…111)	3 bits
1024	10 bits
4096	12 bits
65,536	16 bits

Total memory size (Autumn-25 Q1b, Summer-24)

“IAS has a 12-bit memory address. What is the total capacity — in bits, bytes and words?”

\begin{aligned} \text{Address} &= 12 \text{ bits} \\ \text{Number of rows} &= 2^{12} = 4096 \text{ words} \\ \text{Each row} &= 1 \text{ word} = 40 \text{ bits} \\ \text{Total (bits)} &= 40 \times 2^{12} = 40 \times 4096 = 163{,}840 \text{ bits} \\ \text{Total (bytes)} &= \frac{40 \times 2^{12}}{8} = \frac{163{,}840}{8} = 20{,}480 \text{ bytes} \quad \text{(1 byte = 8 bits)} \\ \text{Total (words)} &= 2^{12} = 4096 \text{ words} \end{aligned}

Answer: 163,840 bits = 20,480 bytes = 4096 words (= 20 KB).

Memory scaling (Autumn-24 Q1b, Spring-26 Q1b)

“If main memory were increased by

2^{n}

times, what is the new address size? What is the max n for which the instruction size would not change?”

Multiplying the number of rows by $2^{n}$ adds n bits to the address:

\begin{aligned} \text{new rows} &= 2^{12} \times 2^{n} = 2^{12+n} \\ \text{new address} &= \log_2(2^{12+n}) = (12 + n) \text{ bits} \end{aligned}

The IAS address field is 12 bits (each instruction = 8-bit opcode + 12-bit address). The instruction format only stays unchanged while the address still fits in 12 bits, i.e.

12 + n \le 12

→ max n = 0. Any growth (

n \ge 1

) needs a wider address field, changing the instruction size.

Memory formats — Figure 1.7

A 40-bit word can hold either a number or two instructions.

(a) Number word (40 bits)

Number word — bit 0 = sign bit, bits 1–39 = the number

(b) Instruction word (40 bits) = TWO instructions

Instruction word — left instruction (20 bits) in bits 0–19, right instruction (20 bits) in bits 20–39

Each instruction = 8-bit opcode + 12-bit address = 20 bits; two of them fill the 40-bit word (left = bits 0–19, right = bits 20–39). Note the 12-bit address field exactly matches the 12-bit address line (4096 rows) — which is why the memory can’t grow without changing the format.