COD Ch.4 — Performance

I.1bigSketch the structure of the IAS computer and name its components.

I.2Calculate the size of the IAS main memory in bits, bytes, and words.

4096 words × 40 bits. Number of rows = $2^{12} = 4096$ .

\begin{aligned} \text{bits} &= 40 \times 2^{12} = 163{,}840 \text{ bits} \\ \text{bytes} &= 163{,}840 / 8 = 20{,}480 \text{ bytes} \\ \text{words} &= 2^{12} = 4096 \text{ words} \end{aligned}

163,840 bits = 20,480 bytes = 4096 words.

I.3Show the IAS memory formats (data and instruction).

I.4bigMemory contents: 08A=…, 08B=…, 08C=…, 08D=…. Write assembly + machine code for M(08D) = M(08C) − M(08A) − M(08B).

Assembly	Opcode	Address
LOAD M(08C)	0000 0001	0000 1000 1100
SUB M(08A)	0000 0110	0000 1000 1010
SUB M(08B)	0000 0110	0000 1000 1011
STOR M(08D)	0010 0001	0000 1000 1101

I.5On the IAS, read a value from address X and write double the value back to X. (Hint: LSH.)

LOAD M(X)      ; AC = M(X)
LSH            ; AC = AC × 2
STOR M(X)      ; M(X) = 2·M(X)

LSH shifts AC left one bit = multiply by 2.

I.6bigIf IAS memory is increased by 2ⁿ times, what is the new address size, and the max n for which the instruction size does not change?

New rows = $2^{12} \times 2^{n} = 2^{12+n}$ , so new address = (12 + n) bits.

The instruction’s address field is 12 bits, so the format is unchanged only while $12 + n \le 12$ → max n = 0. Any increase ( $n \ge 1$ ) needs a wider address field, changing the instruction size.

I.7Name the seven IAS registers and what each holds.

IAS — Practice