The complete reference table (the one printed in the exam’s supplementary sheet). You mainly need LOAD / ADD / SUB / STOR — but know where the others live.
All IAS instructions operate on the accumulator (AC); MQ is the multiply-quotient partner register. M(X) = the 40-bit word at address X. Opcodes are 8 bits.
If AC ≥ 0, next instruction from left half of M(X)
00010000
JUMP + M(X,20:39)
If AC ≥ 0, next instruction from right half of M(X)
Arithmetic
Opcode
Symbolic
Meaning
00000101
ADD M(X)
AC ← AC + M(X)
00000111
ADD |M(X)|
AC ← AC + |M(X)|
00000110
SUB M(X)
AC ← AC − M(X)
00001000
SUB |M(X)|
AC ← AC − |M(X)|
00001011
MUL M(X)
AC×MQ: MSBs → AC, LSBs → MQ
00001100
DIV M(X)
AC ÷ M(X): quotient → MQ, remainder → AC
00010100
LSH
AC × 2 (shift left one bit)
00010101
RSH
AC ÷ 2 (shift right one bit)
Address modify
Opcode
Symbolic
Meaning
00010010
STOR M(X,8:19)
Replace left address field of M(X) with 12 rightmost bits of AC
00010011
STOR M(X,28:39)
Replace right address field of M(X) with 12 rightmost bits of AC
The four you use constantly (memorize the opcodes): LOAD M(X) = 00000001 · ADD M(X) = 00000101 · SUB M(X) = 00000110 · STOR M(X) = 00100001.
Handy for “double the value” questions (Autumn-24 Q1a): LSH multiplies AC by 2. So reading X and writing back double it is: LOAD M(X) → LSH → STOR M(X).